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   &#160;<span id="projectnumber">Version 3.01</span>
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   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
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<div class="title">Peripheral Access</div>  </div>
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<p>Describes naming conventions, requirements, and optional features for accessing peripherals.  
<a href="#details">More...</a></p>
<p>Each peripheral provides a data type definition with a name that is composed of a prefix <b>&lt;<em>device abbreviation&gt;</em>_</b> and the <b>&lt;<em>peripheral name</em>&gt;_</b>, for example <b>LPC_UART</b> for the device <b>LPC</b> and the peripheral <b>UART</b>. The intention is to avoid name collisions caused by short names. If more peripherals exist of the same type, identifiers have a postfix consisting of a digit or letter, for example <b>LPC_UART0</b>, <b>LPC_UART1</b>.</p>
<ul>
<li>The data type definition uses the standard C data types from the ANSI C header file &lt;stdint.h&gt;. IO Type Qualifiers are used to specify the access to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of debug information of peripheral registers and are defined as shown below:<br/>
 <div class="fragment"><pre class="fragment"><span class="preprocessor">  #define   __I     volatile const       </span>
<span class="preprocessor">  #define   __O     volatile             </span>
<span class="preprocessor">  #define   __IO    volatile             </span>
</pre></div></li>
</ul>
<ul>
<li>The following typedef is an example for a UART. &lt;<em>device abbreviation</em>&gt;_UART_TypeDef: defines the generic register layout for all UART channels in a device. <br/>
 <div class="fragment"><pre class="fragment"><span class="keyword">typedef</span> <span class="keyword">struct</span>
{
  <span class="keyword">union </span>{
  __I  uint8_t  RBR;                  <span class="comment">/* Offset: 0x000 (R/ )  Receiver Buffer Register            */</span>
  __O  uint8_t  THR;                  <span class="comment">/* Offset: 0x000 ( /W)  Transmit Holding Register           */</span>
  __IO uint8_t  DLL;                  <span class="comment">/* Offset: 0x000 (R/W)  Divisor Latch LSB                   */</span>
       uint32_t RESERVED0;
  };
  <span class="keyword">union </span>{
  __IO uint8_t  DLM;                  <span class="comment">/* Offset: 0x004 (R/W)  Divisor Latch MSB                   */</span>
  __IO uint32_t IER;                  <span class="comment">/* Offset: 0x004 (R/W)  Interrupt Enable Register           */</span>
  };
  <span class="keyword">union </span>{
  __I  uint32_t IIR;                  <span class="comment">/* Offset: 0x008 (R/ )  Interrupt ID Register               */</span>
  __O  uint8_t  FCR;                  <span class="comment">/* Offset: 0x008 ( /W)  FIFO Control Register               */</span>
  };
  __IO uint8_t  LCR;                  <span class="comment">/* Offset: 0x00C (R/W)  Line Control Register               */</span>
       uint8_t  RESERVED1[7];
  __I  uint8_t  LSR;                  <span class="comment">/* Offset: 0x014 (R/ )  Line Status Register                */</span>
       uint8_t  RESERVED2[7];
  __IO uint8_t  SCR;                  <span class="comment">/* Offset: 0x01C (R/W)  Scratch Pad Register                */</span>
       uint8_t  RESERVED3[3];
  __IO uint32_t ACR;                  <span class="comment">/* Offset: 0x020 (R/W)  Autobaud Control Register           */</span>
  __IO uint8_t  ICR;                  <span class="comment">/* Offset: 0x024 (R/W)  IrDA Control Register               */</span>
       uint8_t  RESERVED4[3];
  __IO uint8_t  FDR;                  <span class="comment">/* Offset: 0x028 (R/W)  Fractional Divider Register         */</span>
       uint8_t  RESERVED5[7];
  __IO uint8_t  TER;                  <span class="comment">/* Offset: 0x030 (R/W)  Transmit Enable Register            */</span>
       uint8_t  RESERVED6[39];
  __I  uint8_t  FIFOLVL;              <span class="comment">/* Offset: 0x058 (R/ )  FIFO Level Register                 */</span>
} LPC_UART_TypeDef;
</pre></div></li>
</ul>
<ul>
<li>To access the registers of the UART defined above, pointers to a register structure are defined. In this example &lt;<em>device abbreviation</em>&gt;_UART# are two pointers to UARTs defined with above register structure. <br/>
 <div class="fragment"><pre class="fragment"><span class="preprocessor">#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )</span>
<span class="preprocessor">#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )</span>
</pre></div></li>
</ul>
<ul>
<li>The registers in the various UARTs can now be referred in the user code as shown below:<br/>
 <div class="fragment"><pre class="fragment">LPC_UART1-&gt;DR   <span class="comment">// is the data register of UART1.</span>
</pre></div></li>
</ul>
<hr/>
<h2><a class="anchor" id="core_cmsis_pal_min_reqs"></a>
Minimal Requirements</h2>
<p>To access the peripheral registers and related function in a device, the files <b><em>device.h</em></b> and <b>core_cm<em>#</em>.h</b> define as a minimum: <br/>
<br/>
</p>
<ul>
<li>The <b>Register Layout Typedef</b> for each peripheral that defines all register names. RESERVED is used to introduce space into the structure for adjusting the addresses of the peripheral registers. <br/>
<br/>
 <b>Example:</b> <div class="fragment"><pre class="fragment"><span class="keyword">typedef</span> <span class="keyword">struct</span>
{
  __IO uint32_t CTRL;                 <span class="comment">/* Offset: 0x000 (R/W)  SysTick Control and Status Register */</span>
  __IO uint32_t LOAD;                 <span class="comment">/* Offset: 0x004 (R/W)  SysTick Reload Value Register       */</span>
  __IO uint32_t VAL;                  <span class="comment">/* Offset: 0x008 (R/W)  SysTick Current Value Register      */</span>
  __I  uint32_t CALIB;                <span class="comment">/* Offset: 0x00C (R/ )  SysTick Calibration Register        */</span>
} <a class="code" href="struct_sys_tick___type.html" title="Structure type to access the System Timer (SysTick).">SysTick_Type</a>;
</pre></div></li>
</ul>
<ul>
<li><b>Base Address</b> for each peripheral (in case of multiple peripherals that use the same <b>register layout typedef</b> multiple base addresses are defined). <br/>
<br/>
 <b>Example:</b> <div class="fragment"><pre class="fragment"><span class="preprocessor">#define SysTick_BASE (SCS_BASE + 0x0010)            </span><span class="comment">/* SysTick Base Address     */</span>    
</pre></div></li>
</ul>
<ul>
<li><b>Access Definitions</b> for each peripheral. In case of multiple peripherals that are using the same <b>register layout typdef</b>, multiple access definitions exist (LPC_UART0, LPC_UART2). <br/>
<br/>
 <b>Example:</b> <div class="fragment"><pre class="fragment"><span class="preprocessor">#define SysTick ((SysTick_Type *) Systick_BASE)    </span><span class="comment">/* SysTick access definition */</span>
</pre></div></li>
</ul>
<p>These definitions allow accessing peripheral registers with simple assignments.</p>
<p><b>Example:</b> <br/>
 </p>
<div class="fragment"><pre class="fragment">SysTick-&gt;CTRL = 0;    
</pre></div><hr/>
<h2><a class="anchor" id="core_cmsis_pal_opts"></a>
Optional Features</h2>
<p>Optionally, the file <b><em>device</em>.h</b> may define:</p>
<ul>
<li>#define constants, which simplify access to peripheral registers. These constants define bit-positions or other specific patterns that are required for programming peripheral registers. The identifiers start with <b>&lt;<em>device abbreviation</em>&gt;_</b> and <b>&lt;<em>peripheral name</em>&gt;_</b>. It is recommended to use CAPITAL letters for such #define constants.</li>
</ul>
<ul>
<li>More complex functions (i.e. status query before a sending register is accessed). Again, these functions start with <b>&lt;<em>device abbreviation</em>&gt;_</b> and <b>&lt;<em>peripheral name</em>&gt;_</b>. </li>
</ul>
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